1. Field of the Invention
The present invention relates to a horizontal contour signal generation circuit in a single chip color camera.
2. Description of the Prior Art
FIG. 12 illustrates the configuration of a conventional signal processing circuit in a single chip CCD (Charge Coupled Device) color camera.
The signal processing circuit comprises two delay circuits 1 and 2, a Y-series (luminance signal series) processing circuit 100, and a C-series (chrominance signal series) processing circuit 200.
The first 1H delay circuit 1 generates a video signal obtained by delaying an input video signal (a CCD output signal) by 1H (one horizontal period). The second 1H delay circuit 2 generates a video signal obtained by further delaying by 1H the video signal which has been delayed by 1H.
The input video signal, the video signal which has been delayed by 1H, and the video signal which has been delayed by 2H are fed to the Y-series processing circuit 100 and are also fed to the C-series processing circuit 200.
The operation of the Y-series processing circuit 100 will be first described.
The input video signal, the video signal which has been delayed by 1H, and the video signal which has been delayed by 2H are fed to a vertical contour correction circuit 101 and are fed to a VLPF (Vertical Low-Pass Filter) 102. The vertical contour correction circuit 101 generates a vertical contour signal (vertical aperture signal) VAP on the basis of the input video signal, the video signal which has been delayed by 1H, and the signal which has been delayed by 2H. The VLPF 102 subjects the input video signal, the video signal which has been delayed by 1H, and the video signal which has been delayed by 2H to vertical low-pass filtering processing.
A signal outputted from the VLPF 102 is fed to a first HLPF (Horizontal Low-Pass Filter) 103, and is fed to a second HLPF 104. Each of the LPFs 103 and 104 subjects a signal outputted from the VLPF 102 to horizontal low-pass filtering processing. The first HLPF 103 is constituted by an LPF composed of a large number of taps, and the second HLPF 104 is constituted by an LPF composed of a small number of taps. The first HLPF 103 has the property of passing a higher frequency component, as compared with the second HLPF 104.
An output Ym of the second HLPF 104 is fed to a horizontal contour correction circuit 105. The horizontal contour correction circuit 105 generates a horizontal contour signal (horizontal aperture signal) HAP on the basis of the output Ym of the second HLPF 104.
The vertical contour signal VAP generated by the vertical contour correction circuit 101 and the horizontal contour signal HAP generated by the horizontal contour correction circuit 105 are added by a first adder 106. An output of the first adder 106 and an output Yh of the first HLPF 103 are added by a second adder 107.
An output of the second adder 107 is fed to a luminance signal processing circuit 108, and is outputted as a luminance signal after a synchronizing signal and a blanking signal are added thereto.
It is preferable that the horizontal contour signal HAP is generated on the basis of a signal whose high frequency component has been removed. Accordingly, the horizontal contour signal HAP is generated on the basis of the output Ym of the second HLPF 104 having the property of not passing a higher frequency component, as compared with the first HLPF 103.
On the other hand, it is preferable that used as a luminance signal to be added to a contour signal which is the sum of the vertical contour signal VAP and the horizontal contour signal HAP is a luminance signal including a high frequency component. Accordingly, the luminance signal Yh outputted from the first HLPF 103 having the property of passing a higher frequency component, as compared with the second HLPF 104, is used.
Description is now made of the operation of the C-series processing circuit 200.
The input video signal, the video signal which has been delayed by 1H, and the video signal which has been delayed by 2H are fed to a color separation circuit 201, where a luminance signal Y1 and chrominance signals Cr and Cb are generated. The luminance signal Y1 and the chrominance signals Cr and Cb which are obtained by the color separation circuit 201 are fed to a chrominance signal processing circuit 202.
The chrominance signal processing circuit 202 includes an RBG matrix circuit, a color difference matrix circuit, and so on, to generate color difference signals (R−Y) and (B−Y). The color difference signals (R−Y) and (B−Y) obtained by the chrominance signal processing circuit 202 are fed to a color encoding circuit 203.
In the color encoding circuit 203, two color carriers between which there is a phase difference of 90° are respectively balance-modulated by the color difference signals (R−Y) and (B−Y) and are synthesized, to generate a chrominance signal.
In the conventional Y-series processing circuit 100, the resolution is lowered in an achromatic portion.